Juniper Networks successfully deployed Ansys’s software to speed production of its high-speed networking chips. (Photo: Ansys/PRNewswire)

May 19, 2022

Juniper Networks reportedly achieved faster design verification of its networking chips via Ansys’s distributed compute platform and hierarchical methodology

PITTSBURGH—Juniper Networks, a developer of products and services that support secure, artificial intelligence (AI)-driven networks, deployed Ansys software to accelerate production of its high-speed networking chips, according to a release from Ansys.

Ansys helps Juniper achieve, in significantly less time, power integrity signoff that is predictively accurate to a high degree. It does so with a massively parallelizable design methodology that achieves greater switching coverage and improved reliability, Ansys said in the release.

“Our broad platform of multiphysics signoff analysis products consistently helps our customers optimize their design performance, while reducing the project and technology risks at the leading edge of semiconductor technology,” said John Lee, vice president and general manager of the semiconductor, electronics, and optics business unit at Ansys, in the release.

Networking chips are some of the largest, most complex chips in the semiconductor industry. They are vital components in data transfer applications, including telecommunications, internet switching, and high-speed data center hardware. Advanced networking products often require the successful integration of multiple sub-chips coming together to form a single system solution.

Juniper faced several challenges while implementing its latest 7nm high-speed networking product. Among them were the capacity to analyze a design with more than 60 billion transistors; the ability to ensure reliable dynamic and static voltage drop (DVD) coverage for possible switching scenarios; and the hierarchical support needed to enable full-system analysis across multiple integrated circuits.

Juniper chose Ansys® RedHawk-SC™’s distributed processing capabilities to significantly accelerate the power integrity signoff for its newest high-performance networking chips. Ansys’s hierarchical Chip Power Model also facilitated high-fidelity power network co-simulation of the chip and package, according to the release.

“Despite the increasing size and complexity of our networking solutions, Ansys RedHawk-SC enabled our design teams to deliver outstanding results,” said Debashis Basu, senior vice president, engineering, at Juniper Networks, in the release. “The software was very easy to distribute in our on-premises cloud via standard memory machines, and its advanced features were crucial in delivering more reliable networking products to market faster.”

Ansys RedHawk-SC is reported to help customers achieve optimal power noise and reliability sign off for digital IP and SoC down to 3nm. Its powerful analytics quickly identify weaknesses and allow what-if explorations to optimize power and performance. The software’s cloud-optimized architecture enables the speed and capacity needed for full-chip analysis, Ansys said in the release.

“Our comprehensive suite of integrated electronics tools quickly solve the power management challenges inherent in today’s ultra-large and complex chip designs,” said John Lee, vice president and general manager of the semiconductor, electronics, and optics business unit at Ansys, in the release. “Ansys RedHawk-SC plays a big part in Juniper’s overarching, cloud-enabled strategy for delivering higher speed and capacity.”

 

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